ARMv7指令介绍
介绍
编码标识
- T1, T2, T3…表示第几个Thumb编码
- A1, A2, A3…表示第几个ARM编码
- E1, E2, E3…表示第几个ThumbEE编码
ADC
立即数
加进位（立即数）将立即数和进位标志值与寄存器值相加，并将结果写入目标寄存器。它可以选择根据结果更新条件标志。
T1(ARMv6T2, ARMv7) ADC{S}<c> <Rd>, <Rn>, #<const>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+---+---------+---+--------+| 1 1 1 1 0 | 1 | 0 | 1 0 1 0 | S | Rn |+----------------+---+---+---------+---+--------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+--------------------+| 0 | imm3 | Rd | imm8 |+---+---------+----------+--------------------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) ADC{S}<c> <Rd>, <Rn>, #<const>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 0+------------+------+---+------------+---+------------+-------------+--------+| cond | 0 0 | 1 | 0 1 0 1 | S | Rn | Rd | imm12 |+------------+------+---+------------+---+------------+-------------+--------+寄存器
T1(ARMv6T2, ARMv7) ADC<c> <Rdn>, <Rm> or ADCS <Rdn>, <Rm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------------+---------+-------+--------+| 0 1 0 0 0 1 | 0 1 0 1 | Rm | Rdn |+-------------------+---------+-------+--------+T2(ARMv6T2, ARMv7) ADC{S}<c>.W <Rd>, <Rn>, <Rm>{, <shift>}
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+---+---------+---+--------+| 1 1 1 1 0 | 0 | 1 | 1 0 1 0 | S | Rn |+----------------+---+---+---------+---+--------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+------+------+--------+| 0 | imm3 | Rd | imm2 | type | Rm |+---+---------+----------+------+------+--------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) ADC{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+------------+------+---+--------+| cond | 0 0 | 0 | 0 1 0 1 | S | Rn | Rd | imm5 | type | 0 | Rm |+------------+------+---+------------+---+------------+-------------+------------+------+---+--------+寄存器移位
A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) ADC{S}<c> <Rd>, <Rn>, <Rm>, <type> <Rs>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+----------+---+------+---+--------+| cond | 0 0 | 0 | 0 1 0 1 | S | Rn | Rd | Rs | 0 | type | 1 | Rm |+------------+------+---+------------+---+------------+-------------+----------+---+------+---+--------+ADD
加法指令
立即数
T1(ARMv4T, ARMv5T*, ARMv6*, ARMv7) ADDS <Rd>, <Rn>, #<imm3> or ADD<c> <Rd>, <Rn>, #<imm3>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------+------+---+---+------+-------+--------+| 0 0 0 | 1 1 | 1 | 0 | imm3 | Rn | Rd |+----------+------+---+---+------+-------+--------+T2(ARMv4T, ARMv5T*, ARMv6*, ARMv7) ADDS <Rdn>, #<imm8> or ADD<c> <Rdn>, #<imm8>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------+------+--------+----------------+| 0 0 1 | 1 0 | Rdn | imm8 |+----------+------+--------+----------------+T3(ARMv6T2, ARMv7) ADD{S}<c>.W <Rd>, <Rn>, #<const>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+---+---------+---+--------+| 1 1 1 1 0 | 1 | 0 | 1 0 0 0 | S | Rn |+----------------+---+---+---------+---+--------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+--------------------+| 0 | imm3 | Rd | imm8 |+---+---------+----------+--------------------+T4(ARMv6T2, ARMv7) ADDW<c> <Rd>, <Rn>, #<imm12>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+---+---------+---+--------+| 1 1 1 1 0 | 1 | 1 | 0 0 0 0 | 0 | Rn |+----------------+---+---+---------+---+--------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+--------------------+| 0 | imm3 | Rd | imm8 |+---+---------+----------+--------------------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) ADD{S}<c> <Rd>, <Rn>, #<const>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 0+------------+------+---+------------+---+------------+-------------+--------+| cond | 0 0 | 1 | 0 1 0 0 | S | Rn | Rd | imm12 |+------------+------+---+------------+---+------------+-------------+--------+寄存器
T1(ARMv4T, ARMv5T*, ARMv6*, ARMv7) ADDS <Rd>, <Rn>, <Rm> or ADD<c> <Rd>, <Rn>, <Rm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------+------+---+---+------+-------+--------+| 0 0 0 | 1 1 | 0 | 0 | Rm | Rn | Rd |+----------+------+---+---+------+-------+--------+T2(ARMv4T, ARMv5T*, ARMv6*, ARMv7) ADD<c> <Rdn>, <Rm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------------+-----+----+-------+--------+| 0 1 0 0 0 1 | 0 0 | DN | Rm | Rdn |+-------------------+-----+----+-------+--------+T3(ARMv6T2, ARMv7) ADD{S}<c>.W <Rd>, <Rn>, <Rm>{, <shift>}
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+------+---------+---+--------+| 1 1 1 0 1 | 0 1 | 1 0 0 0 | S | Rn |+----------------+------+---------+---+--------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+------+------+--------+| 0 | imm3 | Rd | imm2 | type | Rm |+---+---------+----------+------+------+--------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) ADD{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+-------------+------+---+--------+| cond | 0 0 | 0 | 0 1 0 0 | S | Rn | Rd | imm5 | type | 0 | Rm |+------------+------+---+------------+---+------------+-------------+-------------+------+---+--------+寄存器移位
A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) ADD{S}<c> <Rd>, <Rn>, <Rm>, <type> <Rs>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+----------+---+------+---+--------+| cond | 0 0 | 0 | 0 1 0 0 | S | Rn | Rd | Rs | 0 | type | 1 | Rm |+------------+------+---+------------+---+------------+-------------+----------+---+------+---+--------+SP加立即数
T1(ARMv4T, ARMv5T*, ARMv6*, ARMv7) ADD<c> <Rd>, SP, #<imm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+---+----------+--------------------+| 0 0 1 0 | 1 | Rd | imm8 |+------------+---+----------+--------------------+T2(ARMv4T, ARMv5T*, ARMv6*, ARMv7) ADD<c> SP, SP, #<imm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+-------------+----+---------------+| 1 0 1 1 | 0 0 0 0 | 0 | imm7 |+------------+-------------+----+---------------+T3(ARMv6T2, ARMv7) ADD{S}<c>.W <Rd>, SP, #<const>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+---+---------+---+---------+| 1 1 1 1 0 | 1 | 0 | 1 0 0 0 | S | 1 1 0 1 |+----------------+---+---+---------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+--------------------+| 0 | imm3 | Rd | imm8 |+---+---------+----------+--------------------+T4(ARMv6T2, ARMv7) ADDW<c> <Rd>, SP, #<imm12>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+---+---------+---+---------+| 1 1 1 1 0 | 1 | 1 | 0 0 0 0 | 0 | 1 1 0 1 |+----------------+---+---+---------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+--------------------+| 0 | imm3 | Rd | imm8 |+---+---------+----------+--------------------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) ADD{S}<c> <Rd>, SP, #<const>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 0+------------+------+---+------------+---+-------------+-------------+--------+| cond | 0 0 | 1 | 0 1 0 0 | S | 1 1 0 1 | Rd | imm12 |+------------+------+---+------------+---+-------------+-------------+--------+SP加寄存器
T1(ARMv4T, ARMv5T*, ARMv6*, ARMv7) ADD<c> <Rdm>, SP, <Rdm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------------+-----+----+---------+--------+| 0 1 0 0 0 1 | 0 0 | DN | 1 1 0 1 | Rdn |+-------------------+-----+----+---------+--------+T2(ARMv4T, ARMv5T*, ARMv6*, ARMv7) ADD<c> SP, <Rn>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------------+-----+----+---------+--------+| 0 1 0 0 0 1 | 0 0 | 1 | Rm | 1 0 1 |+-------------------+-----+----+---------+--------+T3(ARMv6T2, ARMv7) ADD{S}<c>.W <Rd>, SP, <Rm>{, <shift>}
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+------+---------+---+----------+| 1 1 1 0 1 | 0 1 | 1 0 0 0 | S | 1 1 0 1 |+----------------+------+---------+---+----------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+------+------+--------+| 0 | imm3 | Rd | imm2 | type | Rm |+---+---------+----------+------+------+--------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) ADD{S}<c> <Rd>, SP, <Rm>{, <shift>}
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+-------------+------+---+--------+| cond | 0 0 | 0 | 0 1 0 0 | S | 1 1 0 1 | Rd | imm5 | type | 0 | Rm |+------------+------+---+------------+---+------------+-------------+-------------+------+---+--------+ADR
将一个直接值加到PC值上，形成一个PC相对地址，并将结果写到目标寄存器。
T1(ARMv4T, ARMv5T*, ARMv6*, ARMv7) ADR<c> <Rd>, <label>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------+---+--------+----------------+| 1 0 1 0 | 0 | Rd | imm8 |+-------------+---+--------+----------------+T2(ARMv6T2, ARMv7) ADR<c>.W <Rd>, <label>
label在adr指令前面
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+------------+---+---------+| 1 1 1 1 0 | 1 | 1 0 1 0 1 | 0 | 1 1 1 1 |+----------------+---+------------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+--------------------+| 0 | imm3 | Rd | imm8 |+---+---------+----------+--------------------+T3(ARMv6T2, ARMv7) ADR<c>.W <Rd>, <label>
label在adr指令后面
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+------------+---+---------+| 1 1 1 1 0 | 1 | 1 0 0 0 0 | 0 | 1 1 1 1 |+----------------+---+------------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+--------------------+| 0 | imm3 | Rd | imm8 |+---+---------+----------+--------------------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) ADR<c> <Rd>, <label>
label在adr指令后面
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 0+------------+------+---+------------+---+-------------+-------------+--------+| cond | 0 0 | 1 | 0 1 0 0 | 0 | 1 1 1 1 | Rd | imm12 |+------------+------+---+------------+---+-------------+-------------+--------+A2(ARMv4*, ARMv5T*, ARMv6*, ARMv7) ADR<c> <Rd>, <label>
label在adr指令前面
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 0+------------+------+---+------------+---+-------------+-------------+--------+| cond | 0 0 | 1 | 0 0 1 0 | 0 | 1 1 1 1 | Rd | imm12 |+------------+------+---+------------+---+-------------+-------------+--------+AND
立即数
T1(ARMv6T2, ARMv7) AND{S}<c> <Rd>, <Rn>, #<const>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+---+---------+---+---------+| 1 1 1 1 0 | 1 | 0 | 0 0 0 0 | S | Rn |+----------------+---+---+---------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+--------------------+| 0 | imm3 | Rd | imm8 |+---+---------+----------+--------------------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) AND{S}<c> <Rd>, <Rn>, #<const>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 0+------------+------+---+------------+---+-------------+-------------+--------+| cond | 0 0 | 1 | 0 0 0 0 | S | Rn | Rd | imm12 |+------------+------+---+------------+---+-------------+-------------+--------+寄存器
T1(ARMv4T, ARMv5T*, ARMv6*, ARMv7) ANDS <Rdn>, <Rm> or AND<c> <Rdn>, <Rm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------------+---------+-------+--------+| 0 1 0 0 0 0 | 0 0 0 0 | Rm | Rdn |+-------------------+---------+-------+--------+T2(ARMv6T2, ARMv7) AND{S}<c>.W <Rd>, <Rn>, <Rm>{, <shift>}
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+------+---------+---+----------+| 1 1 1 0 1 | 0 1 | 1 0 0 0 | S | Rn |+----------------+------+---------+---+----------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+------+------+--------+| 0 | imm3 | Rd | imm2 | type | Rm |+---+---------+----------+------+------+--------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) AND{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+-------------+------+---+--------+| cond | 0 0 | 0 | 0 0 0 0 | S | Rn | Rd | imm5 | type | 0 | Rm |+------------+------+---+------------+---+------------+-------------+-------------+------+---+--------+寄存器移位
A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) AND{S}<c> <Rd>, <Rn>, <Rm>, <type> <Rs>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+-----------+---+------+---+--------+| cond | 0 0 | 0 | 0 0 0 0 | S | Rn | Rd | Rs | 0 | type | 1 | Rm |+------------+------+---+------------+---+------------+-------------+-----------+---+------+---+--------+ASR
算术右移
立即数
T1(ARMv4T, ARMv5T*, ARMv6*, ARMv7) ADDS <Rd>, <Rn>, #<imm3> or ADD<c> <Rd>, <Rn>, #<imm3>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------+------+-----------+-------+--------+| 0 0 0 | 1 0 | imm5 | Rm | Rd |+----------+------+-----------+-------+--------+T2(ARMv6T2, ARMv7) ASR{S}<c>.W <Rd>, <Rm>, #<imm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+------+---------+---+---------+| 1 1 1 0 1 | 0 1 | 0 0 1 0 | S | 1 1 1 1 |+----------------+------+---------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+------+-----+--------+| 0 | imm3 | Rd | imm2 | 1 0 | Rm |+---+---------+----------+------+-----+--------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) ASR{S}<c> <Rd>, <Rm>, #<imm>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+-------------+--------+--------+| cond | 0 0 | 0 | 1 1 0 1 | S | 0 0 0 0 | Rd | imm5 | 1 0 0 | Rm |+------------+------+---+------------+---+------------+-------------+-------------+--------+--------+寄存器
T1(ARMv4T, ARMv5T*, ARMv6*, ARMv7) ASRS <Rdn>, <Rm> or ASR<c> <Rdn>, <Rm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------------+---------+-------+--------+| 0 1 0 0 0 0 | 0 1 0 0 | Rm | Rdn |+-------------------+---------+-------+--------+T2(ARMv6T2, ARMv7) ASR{S}<c>.W <Rd>, <Rn>, <Rm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---------+---+-----+---+--------+| 1 1 1 1 1 | 0 1 0 | 0 | 1 0 | S | Rn |+----------------+---------+---+-----+---+--------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+----------+---+-------+--------+| 1 1 1 1 | Rd | 0 | 0 0 0 | Rm |+------------+----------+---+-------+--------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) ASR{S}<c> <Rd>, <Rn>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+-----------+---------+--------+| cond | 0 0 | 0 | 1 1 0 1 | S | 0 0 0 0 | Rd | Rm | 0 1 0 1 | Rn |+------------+------+---+------------+---+------------+-------------+-----------+---------+--------+B
跳转
T1(ARMv4T, ARMv5T*, ARMv6*, ARMv7) B<c> <label>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------+----------+----------------+| 1 1 0 1 | cond | imm8 |+-------------+----------+----------------+T2(ARMv4T, ARMv5T*, ARMv6*, ARMv7) B<c> <label>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+-----------------------+| 1 1 1 0 0 | imm11 |+----------------+-----------------------+T3(ARMv6T2, ARMv7) B<c>.W <label>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+---------+-------------+| 1 1 1 1 0 | S | cond | imm6 |+----------------+---+---------+-------------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------+----+---+----+------------------------+| 1 0 | J1 | 0 | J2 | imm11 |+------+----+---+----+------------------------+T4(ARMv6T2, ARMv7) B<c>.W <label>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+----------------------+| 1 1 1 1 0 | S | imm10 |+----------------+---+----------------------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------+----+---+----+------------------------+| 1 0 | J1 | 1 | J2 | imm11 |+------+----+---+----+------------------------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) B<c> <label
31 30 29 28 27 26 25 24 23 0+------------+-------------+----------------------+| cond | 1 0 1 0 | imm24 |+------------+-------------+----------------------+BFC
清除寄存器的位
T1(ARMv6T2, ARMv7) BFC<c> <Rd>, #<lsb>, #<width>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+-----+-------+---+---------+| 1 1 1 1 0 | 0 | 1 1 | 0 1 1 | 0 | 1 1 1 1 |+----------------+---+-----+-------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+------+---+----------+| 0 | imm3 | Rd | imm2 | 0 | msb |+---+---------+----------+------+---+----------+A1(ARMv6T2, ARMv7) BFC<c> <Rd>, #<lsb>, #<width>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+---------------------+----------------+-------------+-------------+-------+---------+| cond | 0 1 1 1 1 1 0 | msb | Rd | lsb | 0 0 1 | 1 1 1 1 |+------------+---------------------+----------------+-------------+-------------+-------+---------+BFI
位复制
T1(ARMv6T2, ARMv7) BFI<c> <Rd>, <Rn>, #<lsb>, #<width>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+-----+-------+---+---------+| 1 1 1 1 0 | 0 | 1 1 | 0 1 1 | 0 | Rn |+----------------+---+-----+-------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+------+---+----------+| 0 | imm3 | Rd | imm2 | 0 | msb |+---+---------+----------+------+---+----------+A1(ARMv6T2, ARMv7) BFI<c> <Rd>, <Rn>, #<lsb>, #<width>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+---------------------+----------------+-------------+-------------+-------+---------+| cond | 0 1 1 1 1 1 0 | msb | Rd | lsb | 0 0 1 | Rn |+------------+---------------------+----------------+-------------+-------------+-------+---------+BIC
清零对应位
立即数
T1(ARMv6T2, ARMv7) BIC{S}<c> <Rd>, <Rn>, #<const>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+---+---------+---+---------+| 1 1 1 1 0 | 1 | 0 | 0 0 0 1 | S | Rn |+----------------+---+---+---------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+--------------------+| 0 | imm3 | Rd | imm8 |+---+---------+----------+--------------------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) BIC{S}<c> <Rd>, <Rn>, #<const>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 0+------------+------+---+------------+---+-------------+-------------+--------+| cond | 0 0 | 1 | 1 1 1 0 | S | Rn | Rd | imm12 |+------------+------+---+------------+---+-------------+-------------+--------+寄存器
T1(ARMv4T, ARMv5T*, ARMv6*, ARMv7) BICS <Rdn>, <Rm> or BIC<c> <Rdn>, <Rm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------------+---------+-------+--------+| 0 1 0 0 0 0 | 1 1 1 0 | Rm | Rdn |+-------------------+---------+-------+--------+T2(ARMv6T2, ARMv7) BIC{S}<c>.W <Rd>, <Rn>, <Rm>{, <shift>}
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+------+---------+---+----------+| 1 1 1 0 1 | 0 1 | 0 0 0 1 | S | Rn |+----------------+------+---------+---+----------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+------+------+--------+| 0 | imm3 | Rd | imm2 | type | Rm |+---+---------+----------+------+------+--------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) BIC{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+-------------+------+---+--------+| cond | 0 0 | 0 | 1 1 1 0 | S | Rn | Rd | imm5 | type | 0 | Rm |+------------+------+---+------------+---+------------+-------------+-------------+------+---+--------+寄存器移位
A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) BIC{S}<c> <Rd>, <Rn>, <Rm>, <type> <Rs>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+-----------+---+------+---+--------+| cond | 0 0 | 0 | 1 1 1 0 | S | Rn | Rd | Rs | 0 | type | 1 | Rm |+------------+------+---+------------+---+------------+-------------+-----------+---+------+---+--------+BKPT
发生软件断点。
T1(ARMv5T*, ARMv6*, ARMv7) BKPT #<imm8>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+----------+--------------------+| 1 0 1 1 | 1 1 1 0 | imm8 |+------------+----------+--------------------+A1(ARMv5T*, ARMv6*, ARMv7) BKPT #<imm8>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------------------------+--------------------------------------+---------+--------+| cond | 0 0 0 1 0 0 1 0 | imm12 | 0 1 1 1 | imm4 |+------------+------------------------+--------------------------------------+---------+--------+BL,BLX
跳转到对应地址, 如果X存在，则指定指令集的更改(从ARM到Thumb或从Thumb到ARM)。如果省略X，则处理器保持相同的状态。对于ThumbEE指令，不允许指定X。
立即数
T1(ARMv4T, ARMv5T*, ARMv6*, ARMv7 if J1 == J2 == 1) BL<c> <label>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+----------------------+| 1 1 1 1 0 | S | imm10 |+----------------+---+----------------------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------+----+---+----+------------------------+| 1 1 | J1 | 1 | J2 | imm11 |+------+----+---+----+------------------------+T2(ARMv5T*, ARMv6*, ARMv7 if J1 == J2 == 1) BLX<c> <label>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+----------------------+| 1 1 1 1 0 | S | imm10H |+----------------+---+----------------------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------+----+---+----+-----------------------+---+| 1 1 | J1 | 0 | J2 | imm10H | H |+------+----+---+----+-----------------------+---+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) BL<c> <label>
31 30 29 28 27 26 25 24 23 0+------------+-------------+----------------------+| cond | 1 0 1 1 | imm24 |+------------+-------------+----------------------+A2(ARMv4*, ARMv5T*, ARMv6*, ARMv7) BLX <label>
31 30 29 28 27 26 25 24 23 0+------------+---------+----+----------------------+| 1 1 1 1 | 1 0 1 | H | imm24 |+------------+---------+----+----------------------+寄存器
T1(ARMv5T*, ARMv6*, ARMv7) BLX<c> <Rm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------------+-----+---+---------+-------+| 0 1 0 0 0 1 | 1 1 | 1 | Rm | 0 0 0 |+-------------------+-----+---+---------+-------+A1(ARMv5T*, ARMv6*, ARMv7) BLX <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------------------------+-------------------------------------+---------+--------+| cond | 0 0 0 1 0 0 1 0 | 1 1 1 1 1 1 1 1 1 1 1 1 | 0 0 1 1 | Rm |+------------+------------------------+-------------------------------------+---------+--------+BX
带状态切换的跳转
T1(ARMv4T, ARMv5T*, ARMv6*, ARMv7) BX<c> <Rm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------------+-----+---+---------+-------+| 0 1 0 0 0 1 | 1 1 | 0 | Rm | 0 0 0 |+-------------------+-----+---+---------+-------+A1(ARMv4T, ARMv5T*, ARMv6*, ARMv7) BX<c> <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------------------------+-------------------------------------+---------+--------+| cond | 0 0 0 1 0 0 1 0 | 1 1 1 1 1 1 1 1 1 1 1 1 | 0 0 0 1 | Rm |+------------+------------------------+-------------------------------------+---------+--------+BXJ
更改到Jazelle状态。如果尝试失败，它将分支到一个地址和由寄存器指定的指令集，就好像它是一条BX指令一样
T1(ARMv6T2, ARMv7) BXJ<c> <Rm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+---------+-----+---------+| 1 1 1 1 0 | 0 | 1 1 1 1 | 0 0 | Rm |+----------------+---+---------+-----+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------+----+---+----------+-----------------+| 1 0 | 0 | 0 | 1 1 1 1 | 0 0 0 0 0 0 0 0 |+------+----+---+----------+-----------------+A1(ARMv5TEJ, ARMv6*, ARMv7) BXJ<c> <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------------------------+--------------+-------------+-----------+---------+--------+| cond | 0 0 0 1 0 0 1 0 | 1 1 1 1 | 1 1 1 1 | 1 1 1 1 | 0 0 1 0 | Rm |+------------+------------------------+--------------+-------------+-----------+---------+--------+CBNZ, CBZ
非零比较分支和零比较分支将寄存器中的值与零进行比较，并有条件地向前分支一个常量值。它们不影响条件标志
T1(ARMv6T2, ARMv7) CB{N}Z <Rn>, <label>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------+----+---+---+------------+---------+| 1 0 1 1 | op | 1 | 1 | imm5 | Rn |+-------------+----+---+---+------------+---------+CDP,CDP2
告诉协处理器执行一个独立于ARM核心寄存器和内存的操作。如果没有协处理器可以执行该指令，则生成未定义指令异常
T1(ARMv6T2, ARMv7) CDP<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------+----------+---------+---------+| 1 1 1 0 | 1 1 1 0 | opc1 | CRn |+-------------+----------+---------+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+----------+-------+---+--------+| CRd | coproc | opc2 | 0 | CRm |+------------+----------+-------+---+--------+T2(ARMv6T2, ARMv7) CDP2<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------+----------+---------+---------+| 1 1 1 1 | 1 1 1 0 | opc1 | CRn |+-------------+----------+---------+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+----------+-------+---+--------+| CRd | coproc | opc2 | 0 | CRm |+------------+----------+-------+---+--------+A1(RMv4*, ARMv5T*, ARMv6*, ARMv7) CDP<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------------+-----------+--------------+-------------+-----------+-------+---+--------+| cond | 1 1 1 0 | opc1 | CRn | CRd | coproc | opc2 | 0 | CRm |+------------+------------+-----------+--------------+-------------+-----------+-------+---+--------+A2(RMv4*, ARMv5T*, ARMv6*, ARMv7) CDP2<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------------+-----------+--------------+-------------+-----------+-------+---+--------+| cond | 1 1 1 0 | opc1 | CRn | CRd | coproc | opc2 | 0 | CRm |+------------+------------+-----------+--------------+-------------+-----------+-------+---+--------+CHKA
比较两个寄存器中的无符号值。如果第一个小于或等于 其次，它将PC复制到LR，并导致对IndexCheck处理程序的分支
E1 CHKA<c> <Rn>, <Rm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------+----------+---+---------+--------+| 1 1 0 0 | 1 0 1 0 | N | Rm | Rn |+-------------+----------+---+---------+--------+CLREX
清除执行处理器的本地记录，该记录显示某个地址有独占访问请求
T1(ARMv7) CLREX<c>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+-------+-----+---+---------+| 1 1 1 1 0 | 0 | 1 1 1 | 1 0 | 0 | 1 1 1 1 |+----------------+---+-------+-----+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------+----+---+----------+---------+---------+| 1 0 | 0 | 0 | 1 1 1 1 | 0 0 1 0 | 1 1 1 1 |+------+----+---+----------+---------+---------+A1(ARMv6K, ARMv7) CLREX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------------------------+--------------+-------------+-----------+---------+---------+| 1 1 1 1 | 0 1 0 1 0 1 1 1 | 1 1 1 1 | 1 1 1 1 | 0 0 0 0 | 0 0 0 1 | 1 1 1 1 |+------------+------------------------+--------------+-------------+-----------+---------+---------+CLZ
第一个二进制1位之前的二进制零位的个数。
T1(ARMv6T2, ARMv7) CLZ<c> <Rd>, <Rm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+-------+---+-------+---------+| 1 1 1 1 1 | 0 1 0 | 1 | 0 1 1 | Rm |+----------------+-------+---+-------+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+----------+---+-------+---------+| 1 1 1 1 | 1 1 1 1 | 1 | 0 0 0 | Rm |+------------+----------+---+-------+---------+A1(ARMv5T*, ARMv6*, ARMv7) CLZ<c> <Rd>, <Rm>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------------------------+--------------+-------------+-----------+---------+---------+| cond | 0 0 0 1 0 1 1 0 | 1 1 1 1 | Rd | 1 1 1 1 | 0 0 0 1 | Rm |+------------+------------------------+--------------+-------------+-----------+---------+---------+CMN
将立即数或寄存器的值加到对应寄存器, 并根据结果更新程序状态寄存器
立即数
T1(ARMv6T2, ARMv7) CMN<c> <Rn>, #<const>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+---+---------+---+---------+| 1 1 1 1 0 | 1 | 0 | 1 0 0 0 | 1 | Rn |+----------------+---+---+---------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+--------------------+| 0 | imm3 | 1 1 1 1 | imm8 |+---+---------+----------+--------------------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) CMN<c> <Rn>, #<const>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 0+------------+------+---+------------+---+-------------+-------------+--------+| cond | 0 0 | 1 | 1 0 1 1 | 1 | Rn | 0 0 0 0 | imm12 |+------------+------+---+------------+---+-------------+-------------+--------+寄存器
T1(ARMv4T, ARMv5T*, ARMv6*, ARMv7) CMN<c> <Rn>, <Cm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------------+---------+-------+---------+| 0 1 0 0 0 0 | 1 0 1 1 | Rm | Rn |+-------------------+---------+-------+---------+T2(ARMv6T2, ARMv7) CMN<c>.W <Rn>, <Rm>{, <shift>}
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+------+---------+---+---------+| 1 1 1 0 1 | 0 1 | 1 0 0 0 | 1 | Rn |+----------------+------+---------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+------+------+--------+| 0 | imm3 | 1 1 1 1 | imm2 | type | Rm |+---+---------+----------+------+------+--------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) CMN<c> <Rn>, <Rm>{, <shift>}
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+-------------+------+---+--------+| cond | 0 0 | 0 | 1 0 1 1 | 1 | Rn | 0 0 0 0 | imm5 | type | 0 | Rm |+------------+------+---+------------+---+------------+-------------+-------------+------+---+--------+寄存器移位
A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) CMN<c> <Rn>, <Rm>, <type> <Rs>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+-----------+---+------+---+--------+| cond | 0 0 | 0 | 1 0 1 1 | 1 | Rn | 0 0 0 0 | Rs | 0 | type | 1 | Rm |+------------+------+---+------------+---+------------+-------------+-----------+---+------+---+--------+CMP
将寄存器减去立即数或寄存器的值, 并根据结果更新程序状态寄存器
立即数
T1(ARMv4T, ARMv5T*, ARMv6*, ARMv7) CMP<c> <Rn>, #<imm8>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------+------+----------+----------------+| 0 0 1 | 0 1 | Rn | imm8 |+----------+------+----------+----------------+T2(ARMv6T2, ARMv7) CMP<c>.W <Rn>, #<const>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+---+---------+---+---------+| 1 1 1 1 0 | 1 | 0 | 1 1 0 1 | 1 | Rn |+----------------+---+---+---------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+--------------------+| 0 | imm3 | 1 1 1 1 | imm8 |+---+---------+----------+--------------------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) CMP<c> <Rn>, #<const>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 0+------------+------+---+------------+---+-------------+-------------+--------+| cond | 0 0 | 1 | 1 0 1 0 | 1 | Rn | 0 0 0 0 | imm12 |+------------+------+---+------------+---+-------------+-------------+--------+寄存器
T1(ARMv4T, ARMv5T*, ARMv6*, ARMv7) CMP<c> <Rn>, <Cm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------------+---------+-------+---------+| 0 1 0 0 0 0 | 1 0 1 0 | Rm | Rn |+-------------------+---------+-------+---------+T2(ARMv4T, ARMv5T*, ARMv6*, ARMv7) CMP<c> <Rn>, <Cm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------------+-----+---+--------+---------+| 0 1 0 0 0 0 | 0 1 | N | Rm | Rn |+-------------------+-----+---+--------+---------+T3(ARMv6T2, ARMv7) CMP<c>.W <Rn>, <Rm> {, <shift>}
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+------+---------+---+---------+| 1 1 1 0 1 | 0 1 | 1 1 0 1 | 1 | Rn |+----------------+------+---------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+------+------+--------+| 0 | imm3 | 1 1 1 1 | imm2 | type | Rm |+---+---------+----------+------+------+--------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) CMP<c> <Rn>, <Rm>{, <shift>}
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+-------------+------+---+--------+| cond | 0 0 | 0 | 1 0 1 0 | 1 | Rn | 0 0 0 0 | imm5 | type | 0 | Rm |+------------+------+---+------------+---+------------+-------------+-------------+------+---+--------+寄存器移位
A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) CMP<c> <Rn>, <Rm>, <type> <Rs>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+-------------+------+---+--------+| cond | 0 0 | 0 | 1 0 1 0 | 1 | Rn | 0 0 0 0 | Rs | type | 1 | Rm |+------------+------+---+------------+---+------------+-------------+-------------+------+---+--------+CPS
更改一个或多个CPSR。{A, I, F}中断掩码位和CPSR。M模式字段，不改变其他CPSR位
T1(ARMv6*, ARMv7) CPS<effect> <iflags>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------+----------+-------+----+---+---+---+---+| 1 0 1 1 | 0 1 1 0 | 0 1 1 | im | 0 | A | I | F |+-------------+----------+-------+----+---+---+---+---+T2(ARMv6T2, ARMv7) CPS<effect>.W <iflags>{, #<mode>} or CPS #<mode>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+------+---------+---+---------+| 1 1 1 0 1 | 0 1 | 1 1 0 1 | 1 | Rn |+----------------+------+---------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+------+------+--------+| 0 | imm3 | 1 1 1 1 | imm2 | type | Rm |+---+---------+----------+------+------+--------+A1(ARMv6*, ARMv7) CPS<effect> <iflags>{, #<mode>} or CPS #<mode>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------------------------+------+---+---+--------------------+---+---+---+---+-----------+| 1 1 1 1 | 0 0 0 1 0 0 0 0 | imod | M | 0 | 0 0 0 0 0 0 0 | A | I | F | 0 | mode |+------------+------------------------+------+---+---+--------------------+---+---+---+---+-----------+CPY
与mov一样
CSDB
内存屏障，控制投机执行和数据值预测。
T1(ARMv6T2, ARMv7) CSDB{<c>}.W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+-------+-----+---+---------+| 1 1 1 1 0 | 0 | 1 1 1 | 0 1 | 0 | 1 1 1 1 |+----------------+---+-------+-----+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------+----+---+---+-------+---------+---------+| 1 0 | 0 | 0 | 0 | 0 0 0 | 0 0 0 1 | 0 1 0 0 |+------+----+---+---+-------+---------+---------+A1(ARMv6*, ARMv7) CSDB{<c>}
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+---------------+---+------+------------+-------------+-----------+---------+---------+| cond | 0 0 1 1 0 | 0 | 1 0 | 0 0 0 0 | 1 1 1 1 | 0 0 0 0 | 0 0 0 1 | 0 1 0 0 |+------------+---------------+---+------+------------+-------------+-----------+---------+---------+DBG
提供调试和相关系统的提示
T1(ARMv7) DBG<c> #<option>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+-------+-----+---+---------+| 1 1 1 1 0 | 0 | 1 1 1 | 0 1 | 0 | 1 1 1 1 |+----------------+---+-------+-----+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------+----+---+---+-------+---------+---------+| 1 0 | 0 | 0 | 0 | 0 0 0 | 1 1 1 1 | option |+------+----+---+---+-------+---------+---------+A1(ARMv7) DBG<c> #<option>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+---------------+---+------+------------+-------------+-----------+---------+---------+| cond | 0 0 1 1 0 | 0 | 1 0 | 0 0 0 0 | 1 1 1 1 | 0 0 0 0 | 1 1 1 1 | option |+------------+---------------+---+------+------------+-------------+-----------+---------+---------+DMB
数据内存屏障是一种内存屏障，它确保了对内存访问的观察顺序。
T1(ARMv7) DMB<c> <option>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+-------+-----+---+---------+| 1 1 1 1 0 | 0 | 1 1 1 | 0 1 | 1 | 1 1 1 1 |+----------------+---+-------+-----+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------+----+---+----------+---------+---------+| 1 0 | 0 | 0 | 1 1 1 1 | 0 1 0 1 | option |+------+----+---+----------+---------+---------+A1(ARMv7) DMB <option>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------------------------+------------+-------------+-----------+---------+---------+| 1 1 1 1 | 0 1 0 1 0 1 1 1 | 1 1 1 1 | 1 1 1 1 | 0 0 0 0 | 0 1 0 1 | option |+------------+------------------------+------------+-------------+-----------+---------+---------+DSB
数据同步屏障是一种内存屏障，可确保完成内存访问，
T1(ARMv7) DSB<c> <option>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+-------+-----+---+---------+| 1 1 1 1 0 | 0 | 1 1 1 | 0 1 | 1 | 1 1 1 1 |+----------------+---+-------+-----+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------+----+---+----------+---------+---------+| 1 0 | 0 | 0 | 1 1 1 1 | 0 1 0 0 | option |+------+----+---+----------+---------+---------+A1(ARMv7) DSB <option>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------------------------+------------+-------------+-----------+---------+---------+| 1 1 1 1 | 0 1 0 1 0 1 1 1 | 1 1 1 1 | 1 1 1 1 | 0 0 0 0 | 0 1 0 0 | option |+------------+------------------------+------------+-------------+-----------+---------+---------+ENTERX, LEAVEX
ENTERX从Thumb模式到ThumbEE模式, LEAVEX从ThumbEE模式到Thumb模式
ENTERX在Hyp模式没定义
T1(ARMv7) ENTERX or LEAVEX
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-----------------------------+---+---------+| 1 1 1 1 0 0 1 1 1 0 1 | 1 | 1 1 1 1 |+-----------------------------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------+----+---+----------+-------+---+---------+| 1 0 | 0 | 0 | 1 1 1 1 | 0 0 0 | J | 1 1 1 1 |+------+----+---+----------+-------+---+---------+EOR
或操作
立即数
T1(ARMv6T2, ARMv7) EOR{S}<c> <Rd>, <Rn>, #<const>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+-----------+---+---------+| 1 1 1 1 0 | 1 | 0 1 0 0 0 | S | Rn |+----------------+---+-----------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+--------------------+| 0 | imm3 | Rd | imm8 |+---+---------+----------+--------------------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) EOR{S}<c> <Rd>, <Rn>, #<const>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 0+------------+------+---+------------+---+-------------+-------------+--------+| cond | 0 0 | 1 | 0 0 0 1 | S | Rn | Rd | imm12 |+------------+------+---+------------+---+-------------+-------------+--------+寄存器
T1(ARMv4T, ARMv5T*, ARMv6*, ARMv7) EORS <Rdn>, <Rm> or EOR<c> <Rdn>, <Rm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------------+---------+-------+---------+| 0 1 0 0 0 0 | 0 0 0 1 | Rm | Rn |+-------------------+---------+-------+---------+T2(ARMv6T2, ARMv7) EOR{S}<c>.W <Rd>, <Rn>, <Rm>{, <shift>}
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+------+---------+---+---------+| 1 1 1 0 1 | 0 1 | 0 1 0 0 | S | Rn |+----------------+------+---------+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+---+---------+----------+------+------+--------+| 0 | imm3 | Rd | imm2 | type | Rm |+---+---------+----------+------+------+--------+A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) EOR{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+-------------+------+---+--------+| cond | 0 0 | 0 | 0 0 0 1 | S | Rn | Rd | imm5 | type | 0 | Rm |+------------+------+---+------------+---+------------+-------------+-------------+------+---+--------+寄存器移位
A1(ARMv4*, ARMv5T*, ARMv6*, ARMv7) EOR{S}<c> <Rd>, <Rn>, <Rm>, <type> <Rs>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------+---+------------+---+------------+-------------+-----------+---+------+---+--------+| cond | 0 0 | 0 | 0 0 0 1 | S | Rn | Rd | Rs | 1 | type | 1 | Rm |+------------+------+---+------------+---+------------+-------------+-----------+---+------+---+--------+ERET
当在Hyp模式下执行时，Exception Return从ELR_hyp加载PC，从SPSR_hyp加载CPSR。
T1(ARMv6T2, ARMv7, ARMv7VE) SUBS PC, LR, #0(ARMv6T2, ARMv7) or ERET<c>(ARMv7VE)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+----------------+---------+| 1 1 1 1 0 | 0 1 1 1 1 0 1 | 1 1 1 0 |+----------------+----------------+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+----------+--------------------+| 1 0 0 0 | 1 1 1 1 | imm8 |+------------+----------+--------------------+A1(ARMv7VE) ERET<c>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------------------------+-----------------------------------+---------+---------+| cond | 0 0 0 1 0 1 1 0 | 0 0 0 0 0 0 0 0 0 0 0 0 | 0 1 1 0 | 1 1 1 0 |+------------+------------------------+-----------------------------------+---------+---------+HB, HBL
分支到指定的处理程序。
E1 HB{L}<c> #<HandlerID>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+---------+---+------------------+| 1 1 0 0 | 0 0 1 | L | handler |+------------+---------+---+------------------+HBLP
E1 HBLP<c> #<imm>, #<HandlerID>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+-------+----------+-------------+| 1 1 0 0 | 0 1 | imm5 | handler |+------------+-------+----------+-------------+HBP
E1 HBP<c> #<imm>, #<HandlerID>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+-----------+--------+-------------+| 1 1 0 0 | 0 0 0 0 | imm3 | handler |+------------+-----------+--------+-------------+HVC
在执行HVC指令时，HSR使用EC值将异常报告为Hypervisor Call异常 0x12，并捕获立即参数的值
T1(ARMv7VE) HVC #<imm>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+----------------+---------+| 1 1 1 1 0 | 1 1 1 1 1 1 0 | imm4 |+----------------+----------------+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+---------------------------+| 1 0 0 0 | imm12 |+------------+---------------------------+A1(ARMv7VE) HVC #<imm>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------------------------+-----------------------------------+---------+---------+| cond | 0 0 0 1 0 1 0 0 | imm12 | 0 1 1 1 | imm4 |+------------+------------------------+-----------------------------------+---------+---------+ISB
同步屏障刷新处理器中的管道
T1(ARMv7) ISB<c> <option>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+----------------+---+-------+-----+---+---------+| 1 1 1 1 0 | 0 | 1 1 1 | 0 1 | 1 | 1 1 1 1 |+----------------+---+-------+-----+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------+----+---+----------+---------+---------+| 1 0 | 0 | 0 | 1 1 1 1 | 0 1 1 0 | option |+------+----+---+----------+---------+---------+A1(ARMv7) ISB <option>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+------------------------+------------+-------------+-----------+---------+---------+| 1 1 1 1 | 0 1 0 1 0 1 1 1 | 1 1 1 1 | 1 1 1 1 | 0 0 0 0 | 0 1 1 0 | option |+------------+------------------------+------------+-------------+-----------+---------+---------+IT
f-Then使以下至多四条指令(IT块)成为有条件的。IT块中指令的条件与IT指令为块中的第一条指令指定的条件相同，或者相反
T1 IT{<x>{<y>{<z>}}} <firstcond>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+-----------+------------+-------------+| 1 0 1 1 | 1 1 1 1 | firstcond | mask |+------------+-----------+------------+-------------+| IT 指令 | 执行掩码 | 描述 | 条件1 | 条件2 | 条件3 | 条件4 |
|---|---|---|---|---|---|---|
| IT | T | 仅第一条指令条件执行 | T | |||
| ITT | TT | 前两条指令条件执行 | T | T | ||
| ITTE | TTE | 前两条指令条件执行，第三条反向执行 | T | T | E | |
| ITET | TET | 第一条指令条件执行，第二条反向执行，第三条条件执行 | T | E | T | |
| ITTEE | TTEE | 前两条指令条件执行，后两条反向执行 | T | T | E | E |
| ITETT | TETT | 第一条指令条件执行，第二条反向执行，后两条条件执行 | T | E | T | T |
| ITETE | TETE | 第一条指令条件执行，第二条反向执行，第三条条件执行，第四条反向执行 | T | E | T | E |
| ITEE | TEE | 第一条指令条件执行，后两条反向执行 | T | E | E | |
| IT | E | 仅第一条指令反向执行 | E | |||
| ITE | TE | 第一条指令条件执行，第二条反向执行 | T | E | ||
| ITEE | TEE | 第一条指令条件执行，后两条反向执行 | T | E | E | |
| ITTT | TTT | 前三条指令条件执行 | T | T | T | |
| ITTTE | TTTE | 前三条指令条件执行，第四条反向执行 | T | T | T | E |
| ITETTE | TETTE | 第一条指令条件执行，第二条反向执行，后三条条件执行 | T | E | T | T |
| ITEEE | TEEE | 第一条指令条件执行，后三条反向执行 | T | E | E | E |
| ITTTEE | TTTEE | 前三条指令条件执行，最后一条反向执行 | T | T | T | E |
| ITTTT | TTTT | 前四条指令条件执行 | T | T | T | T |
- T 表示 “Then”：指令在条件满足时执行。
- E 表示 “Else”：指令在条件不满足时执行。
LDC,LDC2
加载协处理器将存储器数据从连续存储器地址序列加载到协处理器。
立即数
T1(ARMv6T2, ARMv7) LDC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} or LDC{L}<c> <coproc>, <CRd>, [<Rn>], #+/-<imm> or LDC{L}<c> <coproc>, <CRd>, [<Rn>], <option>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------+--------+---+---+---+---+---+---------+| 1 1 1 0 | 1 1 0 | P | U | D | W | 1 | Rn |+-------------+--------+---+---+---+---+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+----------+--------------------+| CRd | coproc | imm8 |+------------+----------+--------------------+T2(ARMv6T2, ARMv7) LDC2{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} or LDC2{L}<c> <coproc>, <CRd>, [<Rn>], #+/-<imm> or LDC2{L}<c> <coproc>, <CRd>, [<Rn>], <option>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------+--------+---+---+---+---+---+---------+| 1 1 1 1 | 1 1 0 | P | U | D | W | 1 | 1 1 1 1 |+-------------+--------+---+---+---+---+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+----------+--------------------+| CRd | coproc | imm8 |+------------+----------+--------------------+A1(RMv4*, ARMv5T*, ARMv6*, ARMv7) LDC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} or LDC{L}<c> <coproc>, <CRd>, [<Rn>], #+/-<imm> or LDC{L}<c> <coproc>, <CRd>, [<Rn>], <option>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+---------+---+---+---+---+---+------------+-------------+-----------+------------------+| cond | 1 1 0 | P | U | D | W | 1 | Rn | CRd | coproc | imm8 |+------------+---------+---+---+---+---+---+------------+-------------+-----------+------------------+A2(RMv4*, ARMv5T*, ARMv6*, ARMv7) LDC2{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} or LDC2{L}<c> <coproc>, <CRd>, [<Rn>], #+/-<imm> or LDC2{L}<c> <coproc>, <CRd>, [<Rn>], <option>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+---------+---+---+---+---+---+------------+-------------+-----------+------------------+| 1 1 1 1 | 1 1 0 | P | U | D | W | 1 | Rn | CRd | coproc | imm8 |+------------+---------+---+---+---+---+---+------------+-------------+-----------+------------------+字面量
T1(ARMv6T2, ARMv7) LDC{L}<c> <coproc>, <CRd>, <label> or LDC{L}<c> <coproc>, <CRd>, [PC, #-0] or LDC{L}<c> <coproc>, <CRd>, [PC], <option>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------+--------+---+---+---+---+---+---------+| 1 1 1 0 | 1 1 0 | P | U | D | W | 1 | 1 1 1 1 |+-------------+--------+---+---+---+---+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+----------+--------------------+| CRd | coproc | imm8 |+------------+----------+--------------------+T2(ARMv6T2, ARMv7) LDC2{L}<c> <coproc>, <CRd>, <label> or LDC2{L}<c> <coproc>, <CRd>, [PC, #-0] or LD2C{L}<c> <coproc>, <CRd>, [PC], <option>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+-------------+--------+---+---+---+---+---+---------+| 1 1 1 1 | 1 1 0 | P | U | D | W | 1 | 1 1 1 1 |+-------------+--------+---+---+---+---+---+---------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+----------+--------------------+| CRd | coproc | imm8 |+------------+----------+--------------------+A1(RMv4*, ARMv5T*, ARMv6*, ARMv7) LDC{L}<c> <coproc>, <CRd>, <label> or LDC{L}<c> <coproc>, <CRd>, [PC, #-0] or LDC{L}<c> <coproc>, <CRd>, [PC], <option>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+---------+---+---+---+---+---+------------+-------------+-----------+------------------+| cond | 1 1 0 | P | U | D | W | 1 | 1 1 1 1 | CRd | coproc | imm8 |+------------+---------+---+---+---+---+---+------------+-------------+-----------+------------------+A2(RMv4*, ARMv5T*, ARMv6*, ARMv7) LDC2{L}<c> <coproc>, <CRd>, <label> or LDC2{L}<c> <coproc>, <CRd>, [PC, #-0] or LDC2{L}<c> <coproc>, <CRd>, [PC], <option>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+------------+---------+---+---+---+---+---+------------+-------------+-----------+------------------+| 1 1 1 1 | 1 1 0 | P | U | D | W | 1 | 1 1 1 1 | CRd | coproc | imm8 |+------------+---------+---+---+---+---+---+------------+-------------+-----------+------------------+